The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device with a reduced number of intermediate level interconnection patterns and a method of forming the same with a reduced number of processes.
The number of semiconductor devices integrated on a semiconductor integrated circuit chip has been on the increase of about four times per three years. An advanced semiconductor memory device has an integration of more than one hundred million of the semiconductor devices. Such the ultra large scale integrated circuit having the integration of a large number of the semiconductor devices also has a large number of interconnections which inter-connect the semiconductor devices. The ultra large scale integrated circuit has a multilevel interconnection structure, wherein the number of levels of the interconnection layers has been on the increase, for example, up to not less than five levels. In order to increase the density of integration of the large scale integrated circuits, it is necessary to form fine interconnections inter-connecting the individual semiconductor devices and fine contacts connecting the different level interconnections. In addition, it is essential that the multilevel interconnection structure is suitable for increasing the degree of the integration and is formed by an appropriate fabrication method. Usually, the integrated circuit having the multilevel interconnection structure may be fabricated as follows. A first level inter-layer insulator is formed on a semiconductor substrate having semiconductor devices. First level contact holes are formed in the first level inter-layer insulator, so that the first level contact holes reach the semiconductor devices. Conductive layers are filled into the first level contact holes so that first level contact plugs reaching the semiconductor devices are formed in the first level contact holes. First level interconnection layers are formed which extend over the top surface of the first level inter-layer insulator, so that the first level interconnection layers are in contact with top portions of the first level contact plugs in the first level contact holes, whereby the first level interconnection layers are connected through the first level contact plugs to the semiconductor devices on the top surface of the semiconductor substrate. As a result, a first level interconnection structure is completed. In order to form the multilevel interconnection structure, it is necessary to form second, third and further level interconnection structures over the first level interconnection structure in the same manners as described above. Namely, a second level inter-layer insulator is formed on the first level interconnection layers and the first level inter-layer insulator. Second level contact holes are formed in the second level inter-layer insulator, so that the second level contact holes reach the first level interconnection layers. Conductive layers are filled into the second level contact holes so that second level contact plugs reaching the first level interconnection layers are formed in the second level contact holes. Second level interconnection layers are formed which extend over the top surface of the second level inter-layer insulator, so that the second level interconnection layers are in contact with top portions of the second level contact plugs in the second level contact holes, whereby the second level interconnection layers are connected through the second level contact plugs to the first level interconnection layers. As a result, a second level interconnection structure is completed. Further, a third level inter-layer insulator is formed on the second level interconnection layers and the second level inter-layer insulator. Third level contact holes are formed in the third level inter-layer insulator, so that the third level contact holes reach the second level interconnection layers. Conductive layers are filled into the third level contact holes so that third level contact plugs reaching the second level interconnection layers are formed in the third level contact holes. Third level interconnection layers are formed which extend over the top surface of the third level inter-layer insulator, so that the third level interconnection layers are in contact with top portions of the third level contact plugs in the third level contact holes, whereby the third level interconnection layers are connected through the third level contact plugs to the second level interconnection layers. As a result, a third level interconnection structure is completed. Similarly, fourth, fifth and higher level interconnection structures are formed in the same manners. Electrodes are formed on a top inter-layer insulator, so that the electrodes are in contact with the top contact plugs formed in the top contact holes formed in the top inter-layer insulator, whereby the electrodes arc connected through the top contact plugs to the top interconnection layers.
In accordance with the above described first conventional multilevel interconnection structure, the semiconductor devices are connected through all of the multilevel interconnection structures to the electrodes. Namely, the semiconductor devices are connected through all levels of the interconnection layers and the contact plugs to the electrodes, independently from the issue of whether or not it is necessary that the semiconductor devices are connected to any of the intermediate level interconnection layers other than the top level interconnection structures. This means that at least some of the intermediate level interconnection layers are formed for the propose only of indirectly contributing to connect the semiconductor devices on the semiconductor substrate to the electrodes on the top inter-layer insulator, whereby the number of the intermediate level interconnection layers is increased and thereby making it difficult to further increase the density of integration of the integrated circuit having the multilevel interconnection structure.
In order to solve the above problems, a second conventional multilevel interconnection structure was proposed, wherein multilevel contact plugs are connected with each other without intervening the intermediate level interconnection layers. This second conventional multilevel interconnection structure is disclosed in Japanese laid-open patent publication No. 62-130542.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of the second conventional multilevel interconnection structure of the integrated circuit. A first level interconnection layer 101 is formed which extends on a top surface of a silicon substrate 100. A first level inter-layer insulator 102 made of phospho-silicate-glass is entirely formed over the first level interconnection layer 101 and the silicon substrate 100, so that the first level inter-layer insulator 102 covers the first level interconnection layer 101. First level through holes are formed in the first level inter-layer insulator 102, so that the first level through holes reach the first level interconnection layer 101. A conductive metal is filled into the first level through holes to form first level metal contact plugs 103 in the first level through holes in the first level inter-layer insulator 102, so that the first level metal contact plugs 103 are in contact with the first level interconnection layer 101. A second level interconnection layer 105 is formed which extends on a top surface of the first level inter-layer insulator 102, so that the second level interconnection layer 105 is in contact with the tops of some of the first level metal contact plugs 103. A second level inter-layer insulator 104 made of phospho-silicate-glass is entirely formed over the second level interconnection layer 105 and the top surface of the first level inter-layer insulator 102, so that the second level inter-layer insulator 104 covers the second level interconnection layer 105. Second level through holes are formed in the second level inter-layer insulator 104, so that some of the second level through holes reach the second level interconnection layer 105, whilst the remaining ones of the second level through holes are aligned to or reach the tops of the first level metal contact plugs 103 in the first level through holes in the first level inter-layer insulator 102. A conductive metal is filled into the first level through holes to form second level metal contact plugs 106 in the second level through holes in the second level inter-layer insulator 104, so that some of the second level metal contact plugs 106 are in contact with the second level interconnection layer 105, whilst the remaining ones of the second level metal contact plugs 106 are in contact with the tops of the first level metal contact plugs 103 in the first level through holes in the first level inter-layer insulator 102. A third level interconnection layer 107 is formed which extends on a top surface of the second level inter-layer insulator 104, so that the third level interconnection layer 107 is in contact with the second level metal contact plugs 106.
As shown in FIG. 1, some of the second level metal contact plugs 106 are connected through the second level interconnection layer 105 to the first level metal contact plugs 103, whilst the remaining of the second level metal contact plugs 106 are aligned to the remaining of the first level metal contact plugs 103. The remaining of the second level metal contact plugs 106 are directly connected to the remaining of the first level metal contact plugs 103 without intervening the second level interconnection layer 105, whereby it is possible to reduce the necessary number of the interconnection patterns of the second level interconnection layer 105. Namely, the second level interconnection layer 105 does not need to include any interconnection pattern which serves only as an interconnection pad connecting the first level metal contact plug 103 and the second level metal contact plug 106. This contributes to increase the density of the integration of the integrated circuit.
Further, the second level metal contact plug 106 and the second level interconnection layer 105 have the same bottom level as each other. The second level inter-layer insulator 104 has a non-planarized top surface because no planarization process is carried out to the second level inter-layer insulator 104. As a result, the second level inter-layer insulator 104 is uniform in thickness between over the second level interconnection layer 105 and over the first level metal contact plug 103, for which reason the second level through holes formed in the second level inter-layer insulator 104 have the uniform depth between over the second level interconnection layer 105 and over the first level metal contact plug 103. Steps of the second level inter-layer insulator 104 are formed over edges of the interconnection patterns of the second level interconnection layer 105. The second level inter-layer insulator 104 is, however, subjected to a heat treatment to make those steps into slopes. The top surface of the second level inter-layer insulator 104 is never planarized.
FIG. 2 is a fragmentary cross sectional elevation view illustrative of the third conventional multilevel interconnection structure of the integrated circuit. A first level interconnection layer 101 is formed which extends on a top surface of a silicon substrate 100. A first level inter-layer insulator 102 made of phospho-silicate-glass is entirely formed over the first level interconnection layer 101 and the silicon substrate 100, so that the first level inter-layer insulator 102 covers the first level interconnection layer 101. First level through holes are formed in the first level inter-layer insulator 102, so that the first level through holes reach the first level interconnection layer 101. A conductive metal is filled into the first level through holes to form first level metal contact plugs 103 in the first level through holes in the first level inter-layer insulator 102, so that the first level metal contact plugs 103 are in contact with the first level interconnection layer 101. A second level interconnection layer 105 is formed which extends on a top surface of the first level inter-layer insulator 102, so that the second level interconnection layer 105 is in contact with the tops of some of the first level metal contact plugs 103. A second level inter-layer insulator 104 made of phospho-silicate-glass is entirely formed over the second level interconnection layer 105 and the top surface of the first level inter-layer insulator 102, so that the second level inter-layer insulator 104 covers the second level interconnection layer 105. The second level inter-layer insulator 104 is then planarized to form a planarized top surface. The planarization is carried by a chemical mechanical polishing. Second level through holes are formed in the second level inter-layer insulator 104, so that some of the second level through holes reach the second level interconnection layer 105, whilst the remaining ones of the second level through holes are aligned to or reach the tops of the first level metal contact plugs 103 in the first level through holes in the first level inter-layer insulator 102. A conductive metal is filled into the first level through holes to form second level metal contact plugs 106 in the second level through holes in the second level inter-layer insulator 104, so that some of the second level metal contact plugs 106 are in contact with the second level interconnection layer 105, whilst the remaining ones of the second level metal contact plugs 106 are in contact with the tops of the first level metal contact plugs 103 in the first level through holes in the first level inter-layer insulator 102. A third level interconnection layer 107 is formed which extends on a top surface of the second level inter-layer insulator 104, so that the third level interconnection layer 107 is in contact with the second level metal contact plugs 106.
As shown in FIG. 2, some of the second level metal contact plugs 106 are connected through the second level interconnection layer 105 to the first level metal contact plugs 103, whilst the remaining of the second level metal contact plugs 106 are aligned to the remaining of the first level metal contact plugs 103. The remaining of the second level metal contact plugs 106 are directly connected to the remaining of the first level metal contact plugs 103 without intervening the second level interconnection layer 105, whereby it is possible to reduce the necessary number of the interconnection patterns of the second level interconnection layer 105. Namely, the second level interconnection layer 105 does not need to include any interconnection pattern which serves only as an interconnection pad connecting the first level metal contact plug 103 and the second level metal contact plug 106. This contributes to increase the density of the integration of the integrated circuit.
Further, the second level inter-layer insulator 104 has a planarized top surface. As a result, the second level inter-layer insulator 104 is different in thickness between over the second level interconnection layer 105 and over the first level metal contact plug 103, for which reason the second level through holes formed in the second level inter-layer insulator 104 are different in depth between over the second level interconnection layer 105 and over the first level metal contact plug 103.
The above described third conventional semiconductor device as shown in FIG. 2 is disadvantageous in the following viewpoints. The second level contact holes are different in depth between over the first level contact plug 103 and over the second level interconnection layer 105. The second level contact hole positioned over the second level interconnection layer 105 is shallower than the second level contact hole positioned over the first level contact plug 103. Namely, the second level contact hole positioned over the first level contact plug 103 is deeper than the second level contact hole positioned over the second level interconnection layer 105. This means that the second level contact hole positioned over the first level contact plug 103 is higher in aspect ratio than the second level contact hole positioned over the second level interconnection layer 105, wherein the aspect ratio of the through hole is defined to be a depth of the through hole to a diameter of the through hole. The higher aspect ratio of the through hole makes it difficult to realize a perfect or complete etching process to form the through hole and to fill completely the through hole with the metal layer.
Meanwhile, a first conventional method of forming a semiconductor device having a multilevel interconnection structure is proposed and disclosed in Japanese laid-open patent publication No. 11-126820. This first conventional method will be described as follows. Trench isolation films are selectively formed on a semiconductor substrate to define a device formation region surrounded by the trench isolation films. A gate insulation film is formed on the device formation region. A gate electrode is formed on the gate insulation film. Lightly doped regions are selectively formed in the device formation region except under the gate electrode by a first selective ion-implantation using the gate electrode as a mask, wherein the lightly doped regions are self-aligned to the gate electrode. Side wall insulation films are selectively formed on side walls of the gate electrode. Source and drain regions are selectively formed in the device formation region except under the gate electrode and the side wall insulation films by a second selective ion-implantation using the gate electrode and the side wall insulation films as masks, wherein the source and drain regions are self-aligned to the side wall insulation films. As a result, an MOS field effect transistor is formed in the device formation region. A substrate covering film is entirely formed which covers the MOS field effect transistor. A bottom carbon film is formed on the substrate covering film. A bottom silicon dioxide film is formed on the bottom carbon film. A top carbon film is formed on the bottom silicon dioxide film. Interconnection grooves are selectively formed in the top carbon film by a selective anisotropic etching with use of the bottom silicon dioxide film as a stopper. Contact holes are selectively formed which vertically extend from the bottoms of the interconnection grooves to the source and drain regions of the MOS field effect transistor, whereby parts of the source and drain regions are shown through the contact holes. A barrier metal layer is deposited on the shown parts of the source and drain regions and side walls of the contact holes and the bottom of the interconnection groove. A copper layer is also deposited on the barrier metal layer, so that laminations of the barrier metal layer and the copper layer fill both the interconnection groove and the contact holes, whereby interconnections are formed in the interconnection grooves whilst contact plugs are formed in the contact holes. Each of the interconnections and the contact plugs comprises the laminations of the barrier metal layer and the copper layer. The interconnections are connected through the contact plugs to the source and drain regions of the MOS field effect transistor. As a result, a single level interconnection structure has been completed. The above described processes for forming the interconnection structure will be repeated to form a multilevel interconnection structure. A passivation film of silicon dioxide is formed as a top layer over the multilevel interconnection structure. An opening is formed which extends from the silicon dioxide passivation film to the gate electrode of the MOS field effect transistor. An oxygen ashing process to selectively remove the top and bottom carbon films, whereby air-layers are formed around the interconnection and the contact plugs. As a result, the multilevel hollow interconnection structure has been completed.
The first level and second level contact plugs 103 and 106 and the interconnection 105 are formed by two separate processes using independent patterns. Even the contact plugs 103 and 106 and the interconnection 105 are the same in scale or size as each other, then a misalignment or displacement in alignment may be caused in each of the lithography processes, whereby it is possible that the second level contact hole is misaligned to or displaced from the first level contact hole, and namely the second level contact plug 106 is misaligned to or displaced from the first level contact plug 103.
Further, the first level and second level contact plugs 103 and 106 are formed by the two separate processes, for which reason if each of the first level and second level contact plugs 103 and 106 comprises laminations of a barrier metal layer and a conductive metal layer, then the barrier metal layer resides only the side wall of the first level contact hole.
In the above circumstances, it had been required to develop a novel semiconductor device having a multilevel interconnection structure free from the above problems and a method of forming the same.
Accordingly, it is an object of the present invention to provide a novel semiconductor device having a multilevel interconnection structure free from the above problems.
It is a further object of the present invention to provide a novel semiconductor device having a multilevel interconnection structure with reduced necessary number of interconnection patterns serving as interconnection pads in intermediate levels.
It is a still further object of the present invention to provide a novel semiconductor device having a multilevel interconnection structure which allows reducing the necessary number of lithography processes and etching processes for forming intermediate level interconnection structures.
It is yet a further object of the present invention to provide a novel multilevel interconnection structure free from the above problems.
It is further more object of the present invention to provide a novel multilevel interconnection structure with reduced necessary number of interconnection patterns serving as interconnection pads in intermediate levels.
It is still further more object of the present invention to provide a novel multilevel interconnection structure having a multilevel interconnection structure which allows reducing the necessary number of lithography processes and etching processes for forming intermediate level interconnection structures.
It is another object of the present invention to provide a novel method of forming a semiconductor device having a multilevel interconnection structure free from the above problems.
It is further another object of the present invention to provide a novel method of forming a semiconductor device having a multilevel interconnection structure with reduced necessary number of interconnection patterns serving as interconnection pads in intermediate levels.
It is still another object of the present invention to provide a novel method of forming a semiconductor device having a multilevel interconnection structure which allows reducing the necessary number of lithography processes and etching processes for forming intermediate level interconnection structures.
It is yet another object of the present invention to provide a novel method of forming a multilevel interconnection structure free from the above problems.
It is further more another object of the present invention to provide a novel method of forming a multilevel interconnection structure with reduced necessary number of interconnection patterns serving as interconnection pads in intermediate levels.
It is still further more another object of the present invention to provide a novel multilevel interconnection structure having a multilevel interconnection structure which allows reducing the necessary number of lithography processes and etching processes for forming intermediate level interconnection structures.
The present invention provides a multilevel interconnection structure comprising: at least a set of a first lower level contact plug extending in a lower level inter-layer insulator structure and a first higher level contact plug extending in a higher level inter-layer insulator structure extending over the lower level inter-layer insulator structure, wherein a top of the first lower level contact plug is contact directly with a bottom of the first higher level contact plug without intervening any interconnection pad a stopper insulating film extending between the lower level inter-layer insulator structure and the higher level inter-layer insulator structure; and at least a lower-level single conductive united structure which further comprises: a second lower level contact plug extending in the lower level inter-layer insulator structure; and a first lower level interconnection extending in a lower-level interconnection groove formed in an upper region of the lower level inter-layer insulator structure, wherein a top surface of the first lower level interconnection is leveled to a top surface of the lower level inter-layer insulator structure and also leveled to the top of the first lower level contact plug.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.